
CY28551-3
......................Document #: 001-05677 Rev. *D Page 4 of 28
Frequency Select Pins (FS[D:A])
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C, and FS_D
inputs prior to VTT_PWRGD# assertion (as seen by the clock
synthesizer). Upon VTT_PWRGD# being sampled LOW by
the clock chip (indicating processor VTT voltage is stable), the
clock chip samples the FS_A, FS_B, FS_C, and FS_D input
values. For all logic levels of FS_A, FS_B, FS_C, FS_D and
FS_E, VTT_PWRGD# employs a one-shot functionality in that
once a valid LOW on VTT_PWRGD# has been sampled, all
further VTT_PWRGD#, FS_A, FS_B, FS_C, and FS_D transi-
tions will be ignored, except in test mode.
.
Table 1. CPU and SRC Frequency Select Tables
54
*FSB/PCI3
I/O, PU 3.3V-tolerant input for CPU frequency selection/33-MHz clock output. Internal 150k
pull-up
Intel Type-3A output buffer
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications
55
VDDPCI
PWR
3.3V power supply for outputs.
56
*SELP4_K8/PCI3
I/O, PU 3.3V-tolerant input for CPU clock output buffer type selection/33-MHz clock output.
Internal 150k pull-up
Intel Type-3A output buffer
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications
0 = K8 CPU buffer type, 1=P4 CPU buffer type.
Pin Description (continued)
Pin No.
Name
Type
Description
FSD
FSC
FSB
FSA
FSEL3
FSEL2
FSEL1
FSEL0
CPU0
CPU1
SRC
LINK
PCI
CPU
VCO
CPU PLL
Gear
Constant
(G)
CPU
M
CPU
N
PCIE
VCO
SRC PLL
Gear
Constant
PCIE
M
PCIE
N
0000
266.667 266.667
100
66.6667 33.3333
800
80
60
200
800
30
60
200
0001
133.333 133.333
100
66.6667 33.3333
800
40
60
200
800
30
60
200
0010
200
100
66.6667 33.3333
800
60
200
800
30
60
200
0011
166.667 166.667
100
66.6667 33.3333 666.67
60
63
175
800
30
60
200
0100
333.333 333.333
100
66.6667 33.3333 666.67
120
63
175
800
30
60
200
0101
100
66.6667 33.3333
800
30
60
200
800
30
60
200
0110
400
100
66.6667 33.3333
800
120
60
200
800
30
60
200
0111
200
250
100
66.6667 33.3333
1000
60
250
800
30
60
200
1000
266.667 266.667
100
133.333 33.3333
800
80
60
200
800
30
60
200
1001
133.333 133.333
100
133.333 33.3333
800
40
60
200
800
30
60
200
1010
200
100
133.333 33.3333
800
60
200
800
30
60
200
1011
166.667 166.667
100
133.333 33.3333 666.67
60
63
175
800
30
60
200
1100
333.333 333.333
100
133.333 33.3333 666.67
120
63
175
800
30
60
200
1101
100
133.333 33.3333
800
30
60
200
800
30
60
200
1110
400
100
133.333 33.3333
800
120
60
200
800
30
60
200
1111
200
250
100
133.333 33.3333
1000
60
250
800
30
60
200
Frequency Table (ROM)